Multilayer circuits are well known and are typically fabricated by providing a first conductive layer over a substrate, covering the first conductive layer with a dielectric blanket, then providing a second conductive layer over the dielectric blanket. The second conductive layer is circuitized with two photolithographic and wet etching process steps. A first photo pass provides "personality", where circuitry is defined, while a second photo pass is a "select" pass where solderable locations are defined. Vias in the dielectric blanket may be formed either prior to formation of the second conductive layer or after the personality of the second conductive layer is defined.
By way of more specific example, an existing process for producing a circuitized substrate designed to receive an integrated circuit chip might include circuitizing a first metal layer over a substrate, applying a dielectric layer over the first metal layer, forming a second metal layer over the dielectric layer and then personalizing the second metal layer to define individual circuit wires and pads. Conventionally, this personalization of the second metal layer, as well as the first metal layer, comprises a photolithographic etching process. After the second metal layer is personalized, the photoresist is stripped.
Often, the first metal layer and second metal layer will each comprise multiple films or layers. For example, the first metal layer and the second metal layer may each comprise a copper layer with a top film of chromium. This chromium acts as a solder dam for solder bumps to be formed on exposed portions of the first metal layer and the second metal layer. Since the solder bumps must directly contact the copper layer, it is necessary to selectively etch the top chromium films from exposed portions of the first metal layer and the second metal layer. Conventionally, this etching of the chromium films is accomplished by applying a second photoresist layer, which after photolithographic processing, provides openings exposing the areas to be etched and the areas to be laser ablated (to provide vias). The photoresist openings with the vias formed allow the top chromium film of both conductive layers to be etched simultaneously, thereby exposing the underlying copper layers. In a second pass, the second photoresist is stripped from the structure and electrical testing is conducted.
The disadvantage with the above-outlined approach is that consecutive photoresist and wet etching steps occur, each occurrence of which involves a number of processing steps. Further, wet etching chemistry inherently has disposal costs associated therewith.
Thus, the present invention is directed towards providing an improved fabrication method and multilayer circuitized structure which is less complex and costly to manufacture.